ATMEGA640 datasheet(177/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 20-7. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either

of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direc-

tion Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as

output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Gen-

eration mode.

The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled.

Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on

page 182.

20.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes,

setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on

the next compare match. For compare output actions in the non-PWM modes refer to Table 20-5 on page 183. For

fast PWM mode, refer to Table 20-6 on page 183, and for phase correct PWM refer to Table 20-7 on page 184.

A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-

PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits.

20.7 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown

as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock.

The figures include information on when Interrupt Flags are set. Figure 20-8 on page 178 contains timing data for

basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other

than phase correct PWM mode.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

FOCnx

clk

I/O

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