ATMEGA640 datasheet(173/436 Pages) MICROCHIP

173 / 436 page

173

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

20.4.3

Fast PWM Mode

Figure 20-4. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the

interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the

COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting

the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (see Table

20-3 on page 182). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is

set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match

between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is

cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in

the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1

timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the

polarity of the output set by the COM2A1:0 bits).

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle

its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency

of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the

double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

20.4.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform gen-

eration option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly

from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A

when MGM22:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the com-

pare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In

inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

fOCnxPWM

fclk_I/O

N 256



------------------

ATMEGA640 Datasheet(PDF) 173 Page - Microchip Technology

ATMEGA640 Datasheet(HTML) 173 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL