ATMEGA640 datasheet(174/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes,

these modes are preferred for motor control applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter

reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The

timing diagram for the phase correct PWM mode is shown on Figure 20-5. The TCNT2 value is in the timing dia-

gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between

OCR2x and TCNT2.

Figure 20-5. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can

be used to generate an interrupt each time the counter reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the

COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the

COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 20-4

on page 183). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as

output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between

OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match

between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase

correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in

the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set

equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will

have the opposite logic values.

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

fOCnxPCPWM

fclk_I/O

N 510

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ATMEGA640 Datasheet(PDF) 174 Page - Microchip Technology