ATMEGA640 datasheet(201/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 22-1. USART Block Diagram(1)

Note:

1. See Figure 1-1 on page 2, Figure 1-3 on page 4, Table 13-12 on page 80, Table 13-15 on page 82, Table 13-24 on

page 88 and Table 13-27 on page 90 for USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock

Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic con-

sists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate

generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of

a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame

formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is

the most complex part of the USART module due to its clock and data recovery units. The recovery units are used

for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control

logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the

Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.

22.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four

modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave

synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asyn-

chronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in

the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn

pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn

pin is only active when using synchronous mode.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA

UCSRB

UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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