ATMEGA640 datasheet(202/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 22-2 shows a block diagram of the clock generation logic.

Figure 22-2. Clock Generation Logic, Block Diagram

Signal description:

txclk

Transmitter clock (Internal Signal).

rxclk

Receiver base clock (Internal Signal).

xcki

Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master operation.

fOSC

XTAL pin frequency (System Clock).

22.3.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The

description in this section refers to Figure 22-2.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable pres-

caler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value

each time the counter has counted down to zero or when the UBRRLn Register is written. A clock is generated

each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The

Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate genera-

tor output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state

machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn

bits.

Table 22-1 on page 203 contains equations for calculating the baud rate (in bits per second) and for calculating the

UBRRn value for each mode of operation using an internally generated clock source.

Prescaling

Down-Counter

UBRR

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

Detector

UCPOL

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