ATMEGA640 datasheet(213/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

22.7.6

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will there-

fore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal

function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining

data in the buffer will be lost.

22.7.7

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its con-

tents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error

condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to

flush the receive buffer.

Note:

1. See “About Code Examples” on page 10.

22.8 Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The

clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchro-

nous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit,

thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on

the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

22.8.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 22-5 on page 214 illus-

trates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for

Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchro-

nization variation due to the sampling process. Note the larger time variation when using the Double Speed mode

(U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communi-

cation activity).

Assembly Code Example(1)

USART_Flush:

sbis

UCSRnA, RXCn

ret

r16, UDRn

rjmp

USART_Flush

C Code Example(1)

void

USART_Flush( void )

{

unsigned char

dummy;

while

( UCSRnA & (1<<RXCn) ) dummy = UDRn;

}

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