ATMEGA640 datasheet(219/436 Pages) MICROCHIP

219 / 436 page

219

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

22.10.2

UCSRnA – USART Control and Status Register A

• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty

(that is, does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and conse-

quently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see

description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new

data currently present in the transmit buffer (UDRn). The TXCn Flag bit is automatically cleared when a transmit

complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag can generate

a Transmit Complete interrupt (see description of the TXCIEn bit).

• Bit 5 – UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is

empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see

description of the UDRIEn bit).

UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received, that is, when the first stop

bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The

FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two

characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is

valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking

was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to

zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer

rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to one, all the incoming

frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is

unaffected by the MPCMn setting. For more detailed information see “Multi-processor Communication Mode” on

page 216.

Bit

432

RXCn

TXCn

UDREn

FEn

DORn

UPEn

U2Xn

MPCMn

UCSRnA

Read/Write

R/W

Initial Value

000

ATMEGA640 Datasheet(PDF) 219 Page - Microchip Technology

ATMEGA640 Datasheet(HTML) 219 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL