ATMEGA640 datasheet(242/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 24-9. Overview of the TWI Module

24.5.1

SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in

order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes

shorter than 50ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corre-

sponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems

eliminate the need for external ones.

24.5.2

Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in

the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation

does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16

times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the aver-

age TWI bus clock period.

The SCL frequency is generated according to the following equation:

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration detection

Ack

Spike Suppression

Address/Data Shift

SCL frequency

CPU Clock frequency

16 2(TWBR) 4

TWPS



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