ATMEGA640 datasheet(240/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be

wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high

period. The low period of the combined clock is equal to the low period of the Master with the longest low period.

Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods

when the combined SCL line goes high or low, respectively.

Figure 24-7. SCL Synchronization Between Multiple Masters

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read

from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master

can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing

Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA

line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or

address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several

masters are trying to address the same Slave, arbitration will continue into the data packet.

low

high

SCL from

Master A

SCL from

Master B

SCL Bus

Line

low

high

Masters Start

Counting Low Period

Masters Start

Counting High Period

ATMEGA640 Datasheet(PDF) 240 Page - Microchip Technology