ATMEGA640 datasheet(236/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

24. 2-wire Serial Interface

24.1 Features

• Simple yet Powerful and Flexible Communication Interface, only two Bus Lines needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space Allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up When AVR is in Sleep Mode

24.2 2-wire Serial Interface Bus Definition

The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows

the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for

clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up

resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mecha-

nisms for resolving bus contention are inherent in the TWI protocol.

Figure 24-1. TWI Bus Interconnection

24.2.1

TWI Terminology

The following definitions are frequently encountered in this section.

The Power Reduction TWI bit, PRTWI bit in “PRR0 – Power Reduction Register 0” on page 55 must be written to

zero to enable the 2-wire Serial Interface.

Device 1

Device 2

Device 3

Device n

SDA

SCL

........

Table 24-1.

TWI Terminology

Term

Description

Master

The device that initiates and terminates a transmission. The Master also generates the SCL clock

Slave

The device addressed by a Master

Transmitter

The device placing data on the bus

Receiver

The device reading data from the bus

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