ATMEGA640 datasheet(234/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

23.6.3

UCSRnB – USART MSPIM Control and Status Register n B

• Bit 7 - RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated

only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in

UCSRnA is set.

• Bit 6 - TXCIEn: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated

only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCS-

RnA is set.

• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only

if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA

is set.

• Bit 4 - RXENn: Receiver Enable

Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port opera-

tion for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer. Only enabling the receiver

in MSPI mode (that is, setting RXENn=1 and TXENn=0) has no meaning since it is the transmitter that controls the

transfer clock and since only master mode is supported.

• Bit 3 - TXENn: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the

TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until

ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer

port.

• Bit 2:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must

be written to zero when UCSRnB is written.

Bit

7654

3210

RXCIEn

TXCIEn

UDRIE

RXENn

TXENn

UCSRnB

Read/Write

R/W

Initial Value

0000

0110

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