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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

23.6.2

UCSRnA – USART MSPIM Control and Status Register n A

•

• Bit 7 - RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty

(that is, does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and conse-

quently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see

description of the RXCIEn bit).

• Bit 6 - TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new

data currently present in the transmit buffer (UDRn). The TXCn Flag bit is automatically cleared when a transmit

complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag can generate

a Transmit Complete interrupt (see description of the TXCIEn bit).

• Bit 5 - UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is

empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see

description of the UDRIE bit). UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must

be written to zero when UCSRnA is written.

Bit

7654

321

RXCn

TXCn

UDREn

UCSRnA

Read/Write

R/W

Initial Value

0000

011

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