ATMEGA640 datasheet(243/436 Pages) MICROCHIP

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243

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

•

TWBR = Value of the TWI Bit Rate Register

•

TWPS = Value of the prescaler bits in the TWI Status Register

Note:

Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See “2-

wire Serial Interface Characteristics” on page 361 for value of pull-up resistor.

24.5.3

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detec-

tion hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes

received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to

be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However,

when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter

mode, the value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and

STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR

MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master.

If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the

transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is

informed. Correct action can then be taken and appropriate status codes generated.

24.5.4

Address Match Unit

The Address Match unit checks if received address bytes match the seven-bit address in the TWI Address Regis-

ter (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming

address bits will also be compared against the General Call address. Upon an address match, the Control Unit is

informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on set-

tings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (for example, INT0) occurs

during TWI Power-down address match and wakes up the CPU, the TWI aborts operation and return to it’s idle

state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering

Power-down.

24.5.5

Control Unit

The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Reg-

ister (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt

Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code

identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted.

At all other times, the TWSR contains a special status code indicating that no relevant status information is avail-

able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its

tasks before allowing the TWI transmission to continue.

The TWINT Flag is set in the following situations:

•

After the TWI has transmitted a START/REPEATED START condition

•

After the TWI has transmitted SLA+R/W

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After the TWI has transmitted an address byte

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After the TWI has lost arbitration

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After the TWI has been addressed by own slave address or general call

•

After the TWI has received a data byte

•

After a STOP or REPEATED START has been received while still addressed as a Slave

•

When a bus error has occurred due to an illegal START or STOP condition

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