ATMEGA640 datasheet(317/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To

read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When

an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 30-

5 on page 327 for a detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM instruction is executed

within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte

(FHB) will be loaded in the destination register as shown below. Refer to Table 30-4 on page 327 for detailed

description and mapping of the Fuse High byte.

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruction is executed

within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse

byte (EFB) will be loaded in the destination register as shown below. Refer to Table 30-3 on page 326 for detailed

description and mapping of the Extended Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be

read as one.

29.6.10

Reading the Signature Row from Software

To read the Signature Row from software, load the Z-pointer with the signature byte address given in Table 29-5

on page 317 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three

CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the

destination register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row

Lock bits or if no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM

will work as described in the Instruction set Manual.

Note:

All other addresses are reserved for future use.

29.6.11

Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU

and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the

same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write

sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute

instructions incorrectly, if the supply voltage for executing instructions is too low.

Bit

543

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

543

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Bit

543

––

–––

EFB2

EFB1

EFB0

Table 29-5.

Signature Row Addressing

Signature Byte

Z-Pointer Address

Device Signature Byte 1

0x0000

Device Signature Byte 2

0x0002

Device Signature Byte 3

0x0004

RC Oscillator Calibration Byte

0x0001

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