ATMEGA640 datasheet(316/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

ware. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an

interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in

“Interrupts” on page 101.

29.6.5

Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11

unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further soft-

ware updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is

recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software

changes.

29.6.6

Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The

user software itself must prevent that this section is addressed during the self programming operation. The

RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Programming the Interrupt

Vector table should be moved to the BLS as described in “Interrupts” on page 101, or the interrupts must be dis-

abled. Before addressing the RWW section after the programming is completed, the user software must clear the

RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 318 for an

example.

29.6.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write “X0001001” to SPMCSR

and execute SPM within four clock cycles after writing SPMCSR.

See Table 29-2 on page 313 and Table 29-3 on page 313 for how the different settings of the Boot Loader bits

affect the Flash access.

If bits 5:0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction is executed

within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this operation,

but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lOck

bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits.

When programming the Lock bits the entire Flash can be read during the operation.

29.6.8

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock

bits from software will also be prevented during the EEPROM write operation. It is recommended that the user

checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR

29.6.9

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with

0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three

CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the

destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no

(E)LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.

When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set Manual.

Bit

765

4321

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

765

4321

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

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