LPC435X datasheet(7/162 Pages) NXP

7 / 162 page

LPC435X_3X_2X_1X

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Product data sheet

Rev. 5.4 — 10 January 2020

7 of 162

NXP Semiconductors

LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

5. Block diagram

(1) Not available on all parts. See Table 2.

Fig 1.

LPC435x/3x/2x/1x Block diagram

ARM

CORTEX-M4F

TEST/DEBUG

INTERFACE

DMA

LCD(1)

SD/

MMC

ETHERNET(1)

10/100

MAC

IEEE 1588

HIGH-SPEED

USB0(1)

HOST/

DEVICE/OTG

HIGH-SPEED

USB1(1)

HOST/DEVICE

EMC

HIGH-SPEED PHY

SPIFI

HS GPIO

SCT

I2C0

I2S0

I2S1

C_CAN1

MOTOR

CONTROL

PWM(1)

TIMER3

TIMER2

USART2

USART3

SSP1

RI TIMER

QEI(1)

GIMA

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

AHB MULTILAYER MATRIX

LPC435x/3x/2/1x

10-bit ADC0

10-bit ADC1

C_CAN0

I2C1

10-bit DAC

BRIDGE

RGU

CCU2

CGU

CCU1

ALARM TIMER

CONFIGURATION

REGISTERS

OTP MEMORY

EVENT ROUTER

POWER MODE CONTROL

12 MHz IRC

RTC POWER DOMAIN

BACKUP REGISTERS

RTC OSC

RTC

002aah234

slaves

masters

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

= connected to DMA

GPIO

INTERRUPTS

GPIO GROUP0

INTERRUPT

GPIO GROUP1

INTERRUPT

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

SCU

32 kB AHB SRAM

16 kB +

16 kB AHB SRAM

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

512/256 kB FLASH A

512/256 kB FLASH B

16 kB EEPROM

SPI

SGPIO

BRIDGE

slaves

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