ISO1640 datasheet(26/45 Pages) TI

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8.3.3 GPIO Channels

TBD

8.4 Isolator Functional Principle

To isolate a bidirectional signal path (SDA or SCL), the ISO1640 internally splits a bidirectional line into two

unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output

is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1640 connects to a

low-capacitance I2C node (up to 80 pF), while side 2 is designed for connecting to a fully loaded I2C bus with up

to 400 pF of capacitance.

C-out

40 mV

50 mV

SDA1

OL1

IHT1

ILT1

PU1

node

CC1

SDA1

GND1

PU2

bus

CC2

SDA2

GND2

VREF

ISO164x

Figure 8-3. SDA Channel Design and Voltage Levels at SDA1

At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.

However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode

drop to approximately 0.65 V, and the input buffer (C) that consists of a comparator with defined hysteresis.

The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V

(maximum) driven directly by SDA1 and the buffered output low-level of B.

Figure 8-4 demonstrate the switching behavior of the I2C isolator, ISO164x, between a master node at SDA1

and a heavy loaded bus at SDA2.

OL1

IHT1

SDA1

SDA2

SDA1

Transmit

Delay

Transmit

Delay

Receive

Delay

IHT2

50%

30%

Receive

Delay

Receive

Delay

VCC1

VCC2

VCC1

VCC2

OL1

Figure 8-4. SDA Channel Timing in Receive and Transmit Directions

8.4.1 Receive Direction (Left Diagram of Figure 8-4)

When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the

buffered output of VOL1 = 0.65 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum

input-low voltage of VIL = 0.9 V at 3 V supply levels.

When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed

by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the

time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before

SDA2 reaches VCC2 potential.

ISO1640, ISO1641

SLLSFC2B – FEBRUARY 2020 – REVISED MAY 2021

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