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ISO1640 Datasheet(PDF) 28 Page - Texas Instruments

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Part # ISO1640
Description  ISO164x Hot-Swappable Bidirectional I2C Isolators with Enhanced EMC and GPIOs
PDF  45 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ISO1640 Datasheet(HTML) 28 Page - Texas Instruments

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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 I2C Bus Overview
The inter-integrated circuit (I2C) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC
communication in half-duplex mode.
I2C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected
to VDD by resistors (see Figure 9-1). Pulling the line to ground is considered a logic zero while letting the line
float is a logic one. This logic is used as a channel access method. Transitions of logic states must occur while
the SCL pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply
voltages are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.
SDA
SCL
VDD
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
C
Master
C
Slave
GND
GND
GND
SDA
SCL
GND
SDA
SCL
SDA
SCL
SDA
SCL
DAC
Slave
ADC
Slave
Figure 9-1. I2C Bus
I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In practice, however, the number of nodes is limited by the specified,
total bus capacitance of 400 pF, which also restricts communication distances to a few meters.
The specified signaling rates for the ISO164x devices are 100 kbps (standard mode), 400 kbps (fast mode), 1.7
Mbps (fast mode plus).
The bus has two roles for nodes: master and slave. A master node issues the clock and slave addresses,
and also initiates and ends data transactions. A slave node receives the clock and addresses and responds to
requests from the master. Figure 9-2 shows a typical data transfer between master and slave.
ISO1640, ISO1641
SLLSFC2B – FEBRUARY 2020 – REVISED MAY 2021
www.ti.com
28
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: ISO1640 ISO1641



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