MAX17843 datasheet(114/131 Pages) MAXIM

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BIT

POR

NAME

DESCRIPTION

D15

Reserved

Always reads logic-zero.

D14

CBPDIV[2:0]

Sets the step size of the cell-balancing timer LSB per table below:

D13

CBPDIV[2:0]

STEP SIZE

TIMEOUT RANGE

D12

000

Disabled

No timeout

001

1–15s

010

4–60s

011

16s

16–240s

100

64s

64–960s

101

128s

128–1920s

110

256s

256–3840s

111

256s

256–3840s

D11

CBTIMER[3:0]

Watchdog timer for the cell-balancing switches. The timer counts down at a rate set by

CBPDIVn. When the timer reaches ‘0’, all cell-balancing switches are disabled by a signal

separate from the BALCFGn enable bits. The timer should be periodically rewritten with a

timeout value to keep the cell-balancing switches enabled. When the timer value is read,

the value reported is latched during the stop bit time following the ACQCFG UART register

address of the READALL command. If the GPIO3TMR configuration is enabled, the GPIO3

pin is driven high, while CBTIMER[3:0] is nonzero and is driven low when the timer value is

zero. The cell-balancing timer is reset to zero when EMGCYDCHG = 1.

D10

Reserved

Always reads logic-zero.

MAX17843

12-Channel, High-Voltage Smart Sensor

Data-Acquisition Interface

www.maximintegrated.com

Maxim Integrated │ 114

WATCHDOG Register (address 0x18)

MAX17843 Datasheet(PDF) 114 Page - Maxim Integrated Products

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