FXLS93333 datasheet(49/254 Pages) NXP

49 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

TEMP1_ERR

Error condition

No error detected

Over- or Under-Temperature error condition detected

Table 66. Channel 1 temperature sensor error (TEMP1_ERR)

11.2.2.21 Channel 0 temperature sensor error (TEMP0_ERR)

The channel 0 temperature error bit is set if an over or under temperature condition exists

on channel 0. This error is cleared by a read of the DEVSTAT2 register through any

communication interface or on a data transmission that includes the error in the status

field. See Section 11.2.15.2 for details on a method to disable the automatic clearing of

this error in PSI5 mode.

TEMP0_ERR

Error condition

No error detected

Over- or Under-Temperature error condition detected

Table 67. Channel 0 temperature sensor error (TEMP0_ERR)

11.2.2.22 SPI MISO data mismatch error flag (MISO_ERROR)

In SPI mode, the MISO data mismatch flag is set when a MISO Data mismatch fault

occurs as specified in Section 14.5.7. The MISO_ERROR bit is cleared by a read of the

DEVSTAT3 register through any communication interface, or by a status transmission

including the error status through the SPI.

MISO_ERROR

Error condition

Normal operation

MISO Data Mismatch

Table 68. SPI MISO data mismatch error flag (MISO_ERROR)

11.2.2.23 Oscillator training error (OSCTRAIN_ERR)

The oscillator training error bit is set if an error detected in either the oscillator

training settings, or the master communication timing. See Section 11.5.2. Once the

error condition is corrected, the OSCTRAIN_ERR bit is cleared after a read of the

OSCTRAIN_ERR bit through any communication interface, or by a status transmission

including the error status through any communication interface.

OSCTRAIN_ERR

Error condition

No error detected

Oscillator Training Error. See Section 11.5.2

Table 69. Oscillator training error (OSCTRAIN_ERR)

11.2.3 Communication protocol revision register (COMMREV)

The communication protocol revision register is a read-only register which contains the

revision for the communication protocol used.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming

Mode.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

49 / 254

FXLS93333 Datasheet(PDF) 49 Page - NXP Semiconductors

FXLS93333 Datasheet(HTML) 49 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL