FXLS93333 datasheet(65/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.14.4 Command and response mode period (CRM_PER[1:0])

In DSI3 mode, the command and response mode period bits set the period for command

and response mode commands in increments of the periodic data collection mode period

(PDCM_PER). This value is only necessary for DSI3 oscillator training and is only used

if the CK_CAL_EN bit is set in the TIMING_CFG register. command and response mode

commands will be decoded and responded to regardless of the value of this register

as long as the general command and response mode timing parameters specified in

Section 10.11 are met. See Section 11.5.1 for details regarding oscillator training.

In SPI and I2C mode, the CRM_PER[1:0] bits are readable and writable, but have no

impact on device operation or performance.

In PSI5 mode, the CRM_PER[1:0] bits are readable and writable, but have no impact on

device operation or performance.

CRM_PER[1]

CRM_PER[0]

Command and response mode period

(Multiples of the periodic data collection mode period)

Table 98. Command and response mode period (CRM_PER[1:0])

11.2.14.5 Clock calibration enable (CK_CAL_EN)

The clock calibration enable bit enables oscillator training over the DSI3, PSI5, SPI, or

I2C communication interface. See Section 11.5.1 for details regarding oscillator training.

CK_CAL_EN CK_CAL_RST Oscillator training

The oscillator value is maintained at the last trained value prior

to clearing the CK_CAL_RST bit.

The oscillator value is reset to the untrained value with a

tolerance specified in Section 10.20.

Oscillator is trained as specified in Section 11.5.1

Table 99. Clock calibration enable (CK_CAL_EN)

11.2.15 Chip time and bit time register (CHIPTIME)

The chip time and bit time register is a user programmed read/write register which

contains user-specific configuration information. This register is included in the read/write

array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$23

CHIPTIME

ST_RPT[1:0]

PSI5_

ERRLATCH

SS_EN

CHIPTIME[3:0]

Unprogrammed OTP Value

Table 100. Chip time and bit time register (CHIPTIME)

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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