AT25SF321 datasheet(5/48 Pages) DIALOG

Part #	AT25SF321

Description	32-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support

PDF	48 Pages

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Manufacturer	DIALOG [Dialog Semiconductor]

Direct Link	http://www.dialog-semiconductor.com/

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5 / 48 page

AT25SF321

DS-25SF321–047F–8/2017

Block Diagram

Figure 2-1. Block Diagram

Memory Array

To provide the greatest flexibility, the memory array of the AT25SF321 can be erased in four levels of granularity

including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing

both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the

breakdown of each erase level.

Figure 1-1. 8-SOIC (Top View)

Figure 1-2. 8-UDFN (Top View)

GND

VCC

HOLD

SCK

GND

VCC

HOLD

SCK

Flash

Memory

Array

Y-Gating

SCK

Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.

SO (I/O1)

SI (I/O0)

Y-Decoder

X-Decoder

I/O Buffers

and Latches

Control and

Protection Logic

SRAM

Data Buffer

WP (I/O2)

Interface

Control

And

Logic

HOLD (I/O3)

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