AT25SF321 datasheet(35/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

Figure 11-5. Resume from Deep Power-Down and Read Device ID

11.5 Hold Function

The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock

sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program

or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the

erase cycle will continue until it is finished.

If the QE bit value in the Status Register has been set to logical “1”, then the HOLD pin does not function as a control pin.

The HOLD pin will function as an output for Quad-Output Read and input/output for Quad-I/O Read.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the

HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won’t be

started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin

and CS pin are asserted.

While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be

ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If

the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning of the next SCK

low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be

aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.

MSB

10101011

OPCODE

GH-

MPEDANCE

Act

veCur

ent

31 32

38 39

35 36

XXX

MSB

DDDD

AT25SF321 Datasheet(PDF) 35 Page - Dialog Semiconductor