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SLG47503M Datasheet(PDF) 87 Page - Dialog Semiconductor |
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SLG47503M Datasheet(HTML) 87 Page - Dialog Semiconductor |
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87 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 87 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will take maximal 2 ms. Therefore, 8 periods of the Oscillator0 is recommended for the wake time, when BG is configured to Auto Power mode. If low power BG is always on, Oscillator0 period is longer than required wake time. The BG/analog start up time will take maximal 450 us for ACMP0/1. The short wake mode can be used to reduce the current consumption. Figure 71: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used Figure 72: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used Normal ACMP Operation ACMP follows input Sleep Mode ACMP Latches New Data Data is latched BG/Analog Startup time* Force Sleep Sleep Mode ACMP Latches Last Data BG/Analog_Good (internal signal) ACMP_PD is High (From Connection Matrix) CNT_SET (From Connection Matrix) CNT0_out (To Connection Matrix) time between Reset goes low and 1st WS clock rsing edge WS_out (internal signal) Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH. Sleep Mode ACMP Latches New Data Data is latched BG/Analog Startup time* Normal ACMP Operation for short time ACMP follows inout Force Sleep Sleep Mode ACMP Latches Last Data BG/Analog_Good (internal signal) ACMP_PD is High (From Connection Matrix) CNT_RST (From Connection Matrix) CNT0_out (To Connection Matrix) time between Reset goes low and 1st WS clock rsing edge WS_out (internal signal) Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH. |
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