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TC9496AF Datasheet(PDF) 13 Page - Toshiba Semiconductor

Part # TC9496AF
Description  1 Chip Audio Digital Signal Processor
PDF  48 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC9496AF Datasheet(HTML) 13 Page - Toshiba Semiconductor

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TC9496AF
2002-01-11
13
2.2
I
2
C Bus Mode
When I2CS = H, data can be transmitted or received in I2C bus mode.
When the CS signal is Low, control from the microcontroller is enabled.
In I2C mode, the CS signal can be used fixed to L. The IFCK signal is the transmit/receive clock.
The IFDI signal is the data.
The TC9496AF loads the IFDI data on the IFCK signal rising edge.
When CS = H, IFCK and IFD signal are don’t care.
2.2.1 Setting Registers
The register are set by command data using the IFDI signal.
The first byte after the I2C address (= 32h) is a command, which differs for each register. The data
sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C
format.
The data loaded internally every two bytes. Note that commands or data that must be switched on
the SYNC signal, such as the RUN command or the IFF flag, must be synchronized with the SYNC
signal and loaded on that signal.
CS
IFDI
IFCK
C3
C2
C5
C4
C7
C6
C1
C0
A3
A2
A5
A4
A7
A6
A1
A0
D11
D10
D13
D12
D15
D14
D9
D8
An: I
2
C ADDRESS
Cn: COMMAND
Dn: Data
(MCU
®)
start
32h
HZ
HZ
HZ
HZ
end
D3
D2
D5
D4
D7
D6
D1
D0
IFCK



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