HDMP-0421 datasheet(2/12 Pages) HP

Part #	HDMP-0421

Description	Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions

PDF	12 Pages

Scroll/Zoom	100%

Manufacturer	HP [Agilent(Hewlett-Packard)]

Direct Link	http://www.home.agilent.com

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2 / 12 page

The design of the HDMP-0421

allows for placement of the CDR

at one of two locations with

respect to a hard disk slot. For

example, if the BYPASS[0]– pin

is HIGH and hard disk slot A is

connected to PBC cell 1, the CDR

function will be performed before

entering the hard disk at slot A

Figure 2. Timing Waveforms.

Figure 1. Block Diagram of HDMP-0421.

(Figure 4). To achieve a CDR

function after slot A, the

BYPASS[1]– pin must be HIGH

and hard disk slot A must be

connected to PBC cell 0

(Figure 5). Table 2 shows both

possible connections. In both

cases, a Signal Detect (SD) pin

shows the status of the signal at

the incoming cable. The

recommended method of setting

the BYPASS[i]– pins HIGH is to

drive them with a high-

impedence signal. Internal pull-

up resistors will force the

BYPASS[I]– pins to VCC.

(1) FM_NODE[0]

(2) FM_NODE[4]

(1) TO_NODE[0]

(2) TO_NODE[0]

tdelav1.2

LOSDET

TO_NODE[1]

FM_NODE[1]

BYPASS[1]–

SD[1]

IOSDET

SD[0]

CDR

REFCLK

CEXT

BYPASS[0]–

TO_NODE[0]

FM_NODE[0]

HDMP-0421 Datasheet(PDF) 2 Page - Agilent(Hewlett-Packard)

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