LT8722 datasheet(18/30 Pages) AD

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LT8722

Rev. 0

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time limitation, the PWM driver will pulse-skip cycles to

maintain the desired output voltage. The purpose of this

pulse-skipping is to protect the load from over current.

RESET

A reset can be triggered by system fault conditions like a

VDDIO UVLO fault or a thermal shutdown fault. The SPI_

RST bit can be asserted to initiate a reset, via the SPI

interface, if for example an external microcontroller needs

to re-initiate the system. The reset brings all registers to

their default values except for the SPIS_STATUS register.

STATUS MONITORING

LT8722 status is stored in the SPIS_STATUS register

summarized in Table 9. There are six fault bits: OVER_

CURRENT, TSD, VCC_UVLO, VDDIO_UVLO, CP_UVLO

and V2P5_UVLO. To enable the PWM driver and/or the

linear driver, all fault bits must be cleared by writing each

Table 9. SPIS_STATUS Register

BIT NAME

DESCRIPTION

SWEN

1 Indicates That the PWM is Switching

SRVO_ILIM

1 Indicates That the Output Current Limit is Active

SRVO_PLIM

1 Indicates That the Linear Regulator Power

Dissipation Limiting Is Active

MIN_OT

1 Indicates That the PWM Switching Is Limited

By Min-On Or Min-Off Time

POR_OCC

1 is a Latched Indicator That the Reset Has

Happened Since Last Cleared

OVER_CURRENT

1 is a Latched Indicator That the Linear Driver

Overcurrent Fault Has Happened Last Cleared

TSD

1 is a Latched Indicator That the Overtemperature

Fault Has Happened Since Last Cleared

VCC_UVLO

1 is a Latched Indicator That the VCC Regulator

UVLO Fault Has Happened Since Last Cleared

VDDIO_UVLO

1 is a Latched Indicator That the VDDIO Voltage

UVLO Fault Has Happened Since Last Cleared

CP_UVLO

1 is a Latched Indicator That the Charge Pump

UVLO Fault Has Happened Since Last Cleared

V2P5_UVLO

1 is a latched indicator That the 2.5V Reference

UVLO Fault Has Happened Since Last Cleared

ANALOG MONITORING

Several analog signals can be monitored through the

AOUT pin. The signal selection is made in the SPIS_AMUX

0, the AOUT pin is tri-stated. The AMUX_TEST bits can be

used to confirm the AOUT signal integrity by changing the

AOUT pin voltage by a pre-defined amount for the selected

signal. To ensure the most accurate AOUT calculation from

Table 10, be sure to use the most recently measured val-

ues for V1P25 and V1P65.

Table 10. Analog Monitoring

AMUX[3:0] FOR MONITORING

0000

9-bit DAC Voltage, VILIMP for Positive Output Current Limit

0001

9-bit DAC Voltage, VILIMN for Negative Output Current Limit

0010

25-bit DAC Voltage, VDAC

0011

VOUT Voltage Difference, VOUT

0100

IOUT Current Information

0101

Internal Voltage Reference, V2P5

0110

Internal Voltage Reference, V1P25

0111

Internal Voltage Reference, V1P65. AOUT is Equal to V1P65

when Output Current is 0 when this Channel is Selected

1000

Chip Temperature Monitor, VTEMP

1001

VIN Voltage

1010

VCC Voltage

1011

VDDIO Voltage

1100–1101,

1110–1111

VSFB Voltage

The AOUT pin output range is 0.2V to VDDIO–0.2V. The

analog MUX signal range can be beyond the AOUT pin volt-

age range, so some voltage conversions are made. Output

current is transformed to the voltage VIMON which is ide-

ally equal to V1P65 when the output current is 0. When

temperature monitoring is selected, the AOUT pin will

output a voltage proportional to the die temperature with

1.498V (typ) at 25°C and a typical slope of 4.977mV/°C.

Table 11 shows the AOUT pin voltage for various analog

mux signals. The AMUX_TEST bits can change the AOUT

pin output voltage for the same analog mux signal (see

details in Table 12).

OPERATION

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