LTC4151 datasheet(34/82 Pages) AD

34 / 82 page

LTC4284

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

In the high stress staged start mode, either GATE1 low

or GATE2 low sets the FET_BAD_STATUS bit in FAULT_

STATUS register 0x03 and starts the FET bad fault timer.

When the timer expires the FET_BAD_FAULT bit in FAULT

off if the FET_BAD_TURN_OFF bit in CONTROL_1 register

0x0A has been set.

Low Stress Staged Start (Mode 4)

The low stress staged start mode is well suited for appli-

cations with tightly regulated supply voltages. Since in

such a system an input step is no longer a valid operat-

ing condition, the worst-case operating condition for the

MOSFET SOA is charging up the load during startup. By

suppressing the startup inrush current to a very low level,

the SOA demand for the startup MOSFET is greatly allevi-

ated. Additionally, the bypass path only needs inexpen-

sive, switching regulator class MOSFETs. Therefore, this

architecture minimizes the cost of MOSFETs to achieve a

given load current and RDS(ON). However, with the brief

timer delay for current limit, it has limited capability to

ride through an input step or a sustained load surge in

current limit, and due to the low startup current cannot

start up a resistive load such as a heating element or

incandescent lamp.

Figure 13 shows an application circuit for a 2.5kW system

operating in the low stress staged start mode. This mode

is enabled by connecting MODE to INTVCC. In this mode

GATE1 drives a compact, inexpensive MOSFET (M1) with

small SOA as a trickle charging device for startup. GATE2

drives parallel low RDS(ON), low SOA MOSFETs (M2A and

M2B) with a high current limit configured using parallel

small sense resistors to deliver the full load current. The

turn-on sequence is exactly the same as in the high stress

staged start mode as illustrated in Figure 11: GATE1 turns

on first to charge the load and GATE2 turns on after GATE1

is fully enhanced.

Figure 13. –52V/2500W Hot Swap Controller in Low Stress Staged Start Mode with dV/dt Inrush Control: GATE1 Drives

Trickle Startup MOSFET and GATE2 Drives Low RDS(ON) MOSFETs, for Systems with Tightly Regulated Supply Voltages

226k

CVCC

1µF

RS1

M2A

IPT020N10N3

RIN

4 × 1k IN SERIES

0.25W EACH

CIN

0.1µF

M2B

IPT020N10N3

PSMN7R6-100BSE

RG1A

RG1

RG2A

RG2B

100k

10k

RRT

316k

RRB

10.2k

RDT

316k

CG1

10nF

CG2

220nF

2.2nF

2000µF

CUV

10nF

0.33m

RS2

6 × 2m

470nF

412k

10k

COV

10nF

750

RG2

150

RDB

10.2k

26.7k

–52V RTN

UVL

UVH

–52V INPUT

ADIN1-4

TMR

VEE

MODE

INTVCC

SENSE1+

GATE1

GATE2 DRAIN

VIN

RTNS

SCL

SDAI

SDAO

ALERT#

ADIO1-4

PGIO1-4

LTC4284

–52V RTN

(SHORT PIN)

VEE

DRNS

SENSE2+

ADC+

DVDT = 1

THERM_TMR = 0

ILIM = 0011

FB = 10

FB_DIS = 0

LPFB = 0

EN#

UV = 43.4V

UV RELEASE AT 45.1V

OV = 59.3V

OV RELEASE AT 58.3V

VOUT LOW = 44V

VEE

RAMP

VEE

SENSE2–

SENSE1–

ADC–

VEE

VOUTTH

4284 F13

RA1–

RA2–

RA1+

RA2+

LINE OPERATED

(INPUT STEPS LIMITED TO <5V)

VOUT

VLOAD

–

LTC4151 Datasheet(PDF) 34 Page - Analog Devices

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