LTC4151 datasheet(49/82 Pages) AD

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LTC4284

Rev. B

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APPLICATIONS INFORMATION

with 2 (OV) or 2 to 3 (UV) resistors in each divider make it

easier to make non-interactive changes at a later time. The

two dividers as shown in Figure 13 gives UV shutdown at

43.4V, UV release at 45.1V, OV shutdown at 59.3V and

OV release at 58.3V, which covers the full input voltage

range of this example. 10nF capacitors filter out noises

on UVL and OV.

For ADC+ and ADC− inputs, 1Ω is chosen for the averag-

ing resistor on the RS2 side (RA2). The averaging resistor

on the RS1 side is determined by the ratio between RS1

and RS2:

RA1=RA2 •

RS1

RS2

=1Ω •

5mΩ

0.33mΩ

=15Ω

The current ADC has a full scale of 32.768mV. The total

sense resistance is 5mΩ in parallel with six 2mΩ, or

0.312mΩ. With a full scale of 32.768mV on the ADC+ −

ADC− input, this gives a full-scale current of 104.9A and

a LSB size of 25.6mA in 12-bit mode.

Layout Considerations

To achieve accurate current sensing, Kelvin connections

are required. The minimum trace width for 1oz copper

foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider

is recommended. Note that 1oz copper exhibits a sheet

resistance of about 530μΩ/square. Use 2oz or heavier

copper for high current applications.

The VEE pin of the LTC4284 should be connected to a sep-

arate plane from the main –48V input plane. To improve

noise immunity, as shown in Figure 20, the VEE connec-

tions of all capacitors, resistive dividers, opto-isolators

and I2C common must be made directly to the local VEE

plane, not the –48V input plane.

The mechanical stress of soldering a part to a board and

the heat of an IR reflow or convection soldering oven

can cause the ADC full-scale error (FSE) and the current

limit voltage (VILIM) to shift. Refer to Typical Performance

Characteristics for ADC FSE and VILIM shifts of 300 units

of LTC4284 after three cycles of the lead-free IR reflow

process.

Reboot on I2C Command

The LTC4284 features a reboot command bit, RBT_EN

in REBOOT register 0xA2. Setting this bit will cause the

LTC4284 to shut down and reboot after a delay. The

reboot delay is programmable from 512ms to 65.5s

using the three RBT_DL bits in the REBOOT register. A

reboot delay allows load capacitance to fully discharge.

During the reboot delay the DELAY_STATUS bit in the

REBOOT register is set to 1. It will be cleared when the

delay expires. The reboot will also copy the contents of

the EEPROM to volatile registers in the same way as after

initial power-up. On systems where the hot swap con-

troller supplies power to the I2C master, this allows the

master to issue a command that power cycles the entire

board, including itself. Once set, the RBT_EN bit remains

1 after reboot is completed. Clear it before issuing the

next reboot command.

Data Converters

The LTC4284 incorporates a pair of Sigma-Delta A/D con-

verters (ADCs) that are configurable from 8-bit at 1kHz

conversion rate to 16-bit at 1Hz conversion rate in five

settings using the ADC bits in PGIO_CONFIG_2 register

0x11 (see Table 12). In the default continuous mode, the

first ADC (ADC1) continuously monitors the input cur-

rent through a sense resistor between ADC+ and ADC−.

The second ADC (ADC2) is synchronized to ADC1 and

Figure 20. Layout Example of VEE Plane, –48V

Input Plane and Sense Resistor Connection

–48V INPUT PLANE

VEE PLANE

LTC4284 VEE PIN

ALL CAPACITORS

ALL RESISTIVE DIVIDERS

ALL OPTO-ISOLATORS

I2C COMMON

TIE VEE TO –48V INPUT HERE

4248 F20

TO SENSE1–

OR SENSE2– PIN

TO SENSE1+

OR SENSE2+ PIN

MOSFET

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