LTC4151 datasheet(22/82 Pages) AD

22 / 82 page

LTC4284

Rev. B

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APPLICATIONS INFORMATION

During the power-on-reset delay of 1.3ms, the fault regis-

ters are cleared and the control registers are loaded with

the data held in the corresponding EEPROM registers.

The power-on-reset can be detected using the PORB bit

in register 0x0E, which will be cleared when INTVCC dips

below 3.8V. Set this bit to 1 in normal operating condi-

tions and keep monitoring this bit. A 0 from subsequent

reading indicates a power-on-reset has occurred.

Inrush Control

Inrush current control can be configured in two ways.

First, if the DVDT bit in CONTROL_1 register 0x0A is set

to 1, the inrush current is controlled in dV/dt mode by

an external capacitor connected between RAMP and VEE

(the RAMP capacitor, CR), as shown in Figure 6. In dV/dt

mode, the inrush current is limited by controlling a con-

stant output voltage ramp rate (dV/dt). During startup,

when the GATE voltage reaches the MOSFET threshold

voltage, RAMP outputs a fixed 2.5μA current to charge

CR while the inrush current charges load capacitor CL.

During dV/dt control the LTC4284 regulates the RAMP

to the attenuated load voltage between RTNS and DRNS

with an offset:

VRAMP = VRTNS – VDRNS + 0.18V

Figure 5. LTC4284 Turn-On Sequence in Parallel Mode

–48V

INPUT

UVLO AND UV CLEARED

128ms

GATE1

VIN – 1.8V

4284 F05

GATE2

CURRENT

PGIO1

PWRGD1#

READY

PWRGD2#

READY

INTERNAL

POWER

GOOD

INRUSH

(LATCHED)

LOAD1

LOAD1 + LOAD2

MOSFET

VDS

VIN – 1.8V

2.048V

PGIO2

PGIO3

FAULTY POWER GOOD INPUT

NORMAL POWER GOOD INPUT

256ms

512ms

256ms

Figure 6. dV/dt Inrush Control Using RAMP Capacitor

RS1

RIN

CIN

RS2

RRT

200k

RRB

5.11k

RDT

200k

RDB

5.11k

–48V

RTN

–48V

INPUT

VEE

SENSE1– SENSE1+

GATE1

SENSE2–

GATE2

VZ VIN

RTNS

LTC4284

SENSE2+

VEE

RAMP

VLOAD

VOUT

DRNS

–

4284 F06

VEE

LTC4151 Datasheet(PDF) 22 Page - Analog Devices

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