SH7041A datasheet(121/923 Pages) RENESAS

121 / 923 page

When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF.

Even when inputting an external clock, be sure to delay until after the oscillation stabilization time

(upon power-on) or after release from standby, in order to ensure the PLL stabilization time.

EXTAL

XTAL

Open

External clock

input 4–10 MHz

Figure 4.4 Example of External Clock Connection

4.3

Prescaler

The prescaler divides the system clock (

φ) to generate an internal clock (φ/2 to φ/8192) for supply

to peripheral modules.

4.4

Oscillator Halt Function

This CPG can detect a clock halt and automatically cause the timer pins to become high-

impedance when any system abnormality causes the oscillator to halt. That is, when a change of

EXTAL has not been detected, the high-current six pins (PE9/TIOC3B, PE11/TIOC3D,

PE12/TIOC4A, PE13/TIOC4B/

MRES, PE14/TIOC4C/DACK0/AH, PE15/TIOC4D/DACK1/

IRQOUT) are set to high-impedance regardless of PFC setting.

Even in standby mode, these six pins become high-impedance regardless of PFC setting. These

pins enter the normal state after standby mode is cancelled.When abnormalities that halt the

oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI

operations, including these six pins, become undefined even when the oscillator operation starts

again.

4.5

Usage Notes

4.5.1

Oscillator Usage Notes

Since the characteristics of the oscillator are closely related to the user-defined board settings, the

user should refer to the connection examples in this section and perform a careful evaluation. The

oscillator circuit ratings will differ depending on factors such as the oscillator used and the stray

capacitance of the mounted circuitry. Therefore, the oscillator manufacturer should be consulted

before a decision is made. Make sure that the voltage applied to the oscillator does not exceed the

maximum rating.

SH7041A Datasheet(PDF) 121 Page - Renesas Technology Corp