SH7041A datasheet(125/923 Pages) RENESAS

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Section 5 Exception Processing

5.1

Overview

5.1.1

Types of Exception Processing and Priority

Exception processing is started by four sources: resets, address errors, interrupts and instructions

and have the priority shown in table 5.1. When several exception processing sources occur at once,

they are processed according to the priority shown.

Table 5.1

Types of Exception Processing and Priority Order

Exception

Source

Priority

Reset

Power-on reset

High

Manual reset

Address

CPU address error

error

DMAC/DTC address error

Interrupt

NMI

User break

IRQ

On-chip peripheral modules:

• Direct memory access controller (DMAC)

• Multifunction timer/pulse unit (MTU)

• Serial communications interface (SCI)

• A/D converter (A/D)*3

• Data transfer controller (DTC)

• Compare match timer (CMT)

• Watchdog timer (WDT)

• Bus state controller (BSC)

• Port output enable control section

Instructions Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Illegal slot instructions (undefined code placed directly after a delay branch

instruction*

1 or instructions that rewrite the PC*2)

Low

Notes: *1 Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

*2 Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF.

*3 A mask products: A/D0, A/D1.

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