SH7041A datasheet(141/923 Pages) RENESAS

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6.2.4

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral

modules:

• Direct memory access controller (DMAC)

• Multifunction timer/pulse unit (MTU)

• Compare match timer (CMT)

• Serial communications interface (SCI)

• A/D converter (A/D)

• Data transfer controller (DTC)

• Watchdog timer (WDT)

• Bus state controller (BSC)

• I/O port (I/O)

A different interrupt vector is assigned to each interrupt source, so the exception service routine

does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be

assigned to individual on-chip peripheral modules in interrupt priority registers C–H (IPRC–

IPRH).

On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3–I0)

in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that

was accepted.

6.2.5

Interrupt Exception Vectors and Priority Rankings

Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt

priorities.

Each interrupt source is allocated a different vector number and vector table address offset. Vector

table addresses are calculated from vector numbers and address offsets. In interrupt exception

processing, the exception service routine start address is fetched from the vector table indicated by

the vector table address. See table 5.4, Calculating Exception Processing Vector Table Addresses.

IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and

15 for each pin or module by setting interrupt priority registers A–H (IPRA–IPRH). The ranking

of interrupt sources for IPRC–IPRH, however, must be the order listed under Priority Order

Within IPR Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority

level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is

assigned to two or more interrupt sources and interrupts from those sources occur simultaneously,

their priority order is the default priority order indicated at the right in table 6.3.

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