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SH7041A Datasheet(PDF) 138 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 138 Page - Renesas Technology Corp |
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138 / 923 page ![]() 100 CPU SR Interrupt request Com- parator CPU/ DTC request judg- ment Priority ranking judg- ment Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) ISR ICR IPR DTER DTC IPRA–IPRH Module bus Bus interface I3 I2 I1 I0 INTC IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 UBC DMAC MTU CMT SCI A/D DTC (Interrupt request) (Interrupt request) (Interrupt request) WDT BSC I/O UBC: DMAC: MTU: CMT: SCI: A/D: DTC: WDT: BSC: User break controller Direct memory access controller Multifunction timer pulse unit Compare match timer Serial communication interface A/D converter Data transfer controller Watchdog timer Bus state controller (DRAM refresh control section) I/O: ICR: ISR: DTER: IPRA–IPRH: SR: I/O port (port output control section) Interrupt control register IRQ ststus register DTC enable register Interrupt priority level setting registers A to H Status register Figure 6.1 INTC Block Diagram |
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