SH7041A datasheet(134/923 Pages) RENESAS

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5.5.3

General Illegal Instructions

When undefined code placed anywhere other than immediately after a delayed branch instruction

(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The

CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of

illegal slot instructions, however, the program counter value stored is the start address of the

undefined code.

5.6

When Exception Sources Are Not Accepted

When an address error or interrupt is generated after a delayed branch instruction or interrupt-

disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in

table 5.10. When this happens, it will be accepted when an instruction that can accept the

exception is decoded.

Table 5.10

Generation of Exception Sources Immediately after a Delayed Branch

Instruction or Interrupt-Disabled Instruction

Exception Source

Point of Occurrence

Address Error

Interrupt

Immediately after a delayed branch instruction*

Not accepted

Immediately after an interrupt-disabled instruction*

Accepted

Not accepted

Notes: *1 Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

*2 Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L

5.6.1

Immediately after a Delayed Branch Instruction

When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,

neither address errors nor interrupts are accepted. The delayed branch instruction and the

instruction located immediately after it (delay slot) are always executed consecutively, so no

exception processing occurs during this period.

5.6.2

Immediately after an Interrupt-Disabled Instruction

When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts

are not accepted. Address errors are accepted.

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