SH7041A datasheet(132/923 Pages) RENESAS

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5.4.1

Interrupt Priority Level

The interrupt priority order is predetermined. When multiple interrupts occur simultaneously

(overlap), the interrupt controller (INTC) determines their relative priorities and starts up

processing according to the results.

The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and

priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always

accepted. The user break interrupt priority level is 15. IRQ interrupts and on-chip peripheral

module interrupt priority levels can be set freely using the INTC’s interrupt priority level setting

registers A through H (IPRA–IPRH) as shown in table 5.8. The priority levels that can be set are

0–15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers A-H (IPRA-IPRH), for

more information on IPRA to IPRH.

Table 5.8

Interrupt Priority Order

Type

Priority Level

Comment

NMI

Fixed priority level. Cannot be masked.

User break

Fixed priority level.

IRQ

0–15

Set with interrupt priority level setting registers A

through H (IPRA–IPRH).

On-chip peripheral module

0–15

Set with interrupt priority level setting registers A

through H (IPRA–IPRH).

5.4.2

Interrupt Exception Processing

When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI

is always accepted, but other interrupts are only accepted if they have a priority level higher than

the priority level set in the interrupt mask bits (I3–I0) of the status register (SR).

When an interrupt is accepted, exception processing begins. In interrupt exception processing, the

CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted

interrupt is written to SR bits I3–I0. For NMI, however, the priority level is 16, but the value set in

I3–I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the

exception processing vector table for the accepted interrupt, that address is jumped to and

execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt

exception processing.

5.5

Exceptions Triggered by Instructions

Exception processing can be triggered by trap instructions, general illegal instructions, and illegal

slot instructions, as shown in table 5.9.

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