SH7041A datasheet(131/923 Pages) RENESAS

131 / 923 page

5.3.1

Address Error Exception Processing

When an address error occurs, the bus cycle in which the address error occurred ends. When the

executing instruction then finishes, address error exception processing starts up. The CPU operates

as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

3. The exception service routine start address is fetched from the exception processing vector

table that corresponds to the address error that occurred and the program starts executing from

that address. The jump that occurs is not a delayed branch.

5.4

Interrupts

Table 5.7 shows the sources that start up interrupt exception processing. These are divided into

NMI, user breaks, IRQ, and on-chip peripheral modules.

Table 5.7

Interrupt Sources

Type

Request Source

Number of

Sources

NMI

NMI pin (external input)

User break

User break controller

IRQ

IRQ0–IRQ7 (external input)

On-chip peripheral module

Direct memory access controller (DMAC)

Multifunction timer/pulse unit (MTU)

Serial communications interface (SCI)

A/D converter

Data transfer controller (DTC)

Compare match timer (CMT)

Watchdog timer (WDT)

Bus state controller (BSC)

Port

Note: * For A mask products, (A/D0, A/D1) is 2

Each interrupt source is allocated a different vector number and vector table offset. See section 6,

Interrupt Controller (INTC), and table 6.3, Interrupt Exception Processing Vectors and Priorities,

for more information on vector numbers and vector table address offsets.

SH7041A Datasheet(PDF) 131 Page - Renesas Technology Corp