SH7041A datasheet(166/923 Pages) RENESAS

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7.3.2

Break on On-Chip Memory Instruction Fetch Cycle

On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in 1 bus cycle.

Therefore, 2 instructions can be retrieved in 1 bus cycle when fetching instructions from on-chip

memory. At such times, only 1 bus cycle is generated, but by setting the start addresses of both

instructions in the user break address register (UBAR) it is possible to cause independent breaks.

In other words, when wanting to effect a break using the latter of two addresses retrieved in 1 bus

cycle, set the start address of that instruction in UBAR. The break will occur after execution of the

former instruction.

7.3.3

Program Counter (PC) Values Saved

Break on Instruction Fetch (Before Execution): The program counter (PC) value saved to the

stack in user break interrupt exception processing is the address that matches the break condition.

The user break interrupt is generated before the fetched instruction is executed. If a break

condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction

(delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user

break interrupt is not accepted immediately, but the break condition establishing instruction is

executed. The user break interrupt is accepted after execution of the instruction that has accepted

the interrupt. In this case, the PC value saved is the start address of the instruction that will be

executed after the instruction that has accepted the interrupt.

Break on Data Access (CPU/Peripheral): The program counter (PC) value is the top address of

the next instruction after the last instruction executed before the user break exception processing

started. When data access (CPU/peripheral) is set as a break condition, the place where the break

will occur cannot be specified exactly. The break will occur at the instruction fetched close to

where the data access that is to receive the break occurs.

7.4

Use Examples

7.4.1

Break on CPU Instruction Fetch Cycle

1. Register settings:

UBARH = H'0000

UBARL = H'0404

UBBR = H'0054

Conditions set:

Address: H'00000404

Bus cycle: CPU, instruction fetch, read

(operand size not included in conditions)

A user break interrupt will occur before the instruction at address H'00000404. If it is possible for

the instruction at H'00000402 to accept an interrupt, the user break exception processing will be

executed after execution of that instruction. The instruction at H'00000404 is not executed. The

PC value saved is H'00000404.

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