LTM4657 datasheet(6/24 Pages) AD

6 / 24 page

LTM4705

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

FREQ (A4): Frequency is set internally to 1MHz. An exter-

nal resistor can be placed from this pin to GND to increase

frequency, or from this pin to INTVCC to reduce frequency.

See the Applications Information section for frequency

adjustment.

RUN1 (A5), RUN2 (A3): Run Control Input of Each

Switching Mode Regulator Channel. Enables chip opera-

tion by tying RUN above 1.27V. Tying this pin below 1V

shuts down the specific regulator channel. Do not float

this pin.

COMP1 (A6), COMP2 (A2): Current Control Threshold

and Error Amplifier Compensation Point of each Switching

Mode Regulator Channel. The current comparator’s trip

threshold is linearly proportional to this voltage, whose

normal range is from 0.3V to 1.8V. Tie the COMP pins

together for parallel operation. The device is internally

compensated.

FB1 (A7), FB2 (A1): The Negative Input of the Error

Amplifier for Each Switching Mode Regulator Channel.

Internally, this pin is connected to VOUT with a 60.4k preci-

sion resistor. Different output voltages can be programmed

with an additional resistor between FB and GND pins. In

PolyPhase operation, tying the FB pins together allows

for parallel operation. See the Applications Information

section for details.

GND (B3, C2, C3, C5, C6, D4, E1, E4, E7, F1 - F7, G1

- G7, H4, J4): Power Ground Pins for Both Input and

Output Returns.

INTVCC (B4): Internal 3.3V Regulator Output of the

Switching Mode Regulator Channel. The internal power

drivers and control circuits are powered from this voltage.

This pin is internally decoupled to GND with a 2.2µF low

ESR ceramic capacitor. No additional external decoupling

capacitor is needed.

SYNC/MODE (B5): Mode Select and External

Synchronization Input. Tie this pin to ground to force

continuous synchronous operation at all output loads.

Floating this pin or tying it to INTVCC enables high effi-

ciency Burst Mode operation at light loads. Drive this

pin with a clock to synchronize the LTM4705 switching

frequency. An internal phase-locked loop will force the

bottom power N-channel MOSFET’s turn on signal to be

synchronized with the rising edge of the clock signal.

When this pin is driven with a clock, forced continuous

mode is automatically selected.

PGOOD1 (B6), PGOOD2 (B2): Output Power Good with

Open-Drain Logic of Each Switching Mode Regulator

Channel. PGOOD is pulled to ground when the voltage

on the FB pin is not within ±8% (typical) of the internal

0.6V reference.

TRACK/SS1 (B7), TRACK/SS2 (B1): Output Tracking and

Soft-Start Pin of Each Switching Mode Regulator Channel.

It allows the user to control the rise time of the output

voltage. Putting a voltage below 0.6V on this pin bypasses

the internal reference input to the error amplifier, instead

it servos the FB pin to the TRACK voltage. Above 0.6V,

the tracking function stops and the internal reference

resumes control of the error amplifier. There’s an internal

1.4µA pull-up current from INTVCC on this pin, so putting

a capacitor here provides soft-start function.

SGND (C4): Signal Ground Connection. Tie to GND with

minimum distance. Connect COMP component, MODE,

TRACK/SS component, FB resistor to this pin as needed.

VIN1 (C7, D5 - D7, E5 - E6), VIN2 (C1, D1 - D3, E2 - E3):

Power Input Pins. Apply input voltage between these pins

and GND pins. Recommend placing input decoupling

capacitance directly between BOTH VIN1 and VIN2 pins

and GND pins. Please note the module internal control cir-

cuitry is running off VIN1. Channel 2 will not work without

a voltage higher than 3.1V present at VIN1.

VOUT1 (H5 - H7, J5 - J7), VOUT2 (H1 - H3, J1 - J3): Power

Output Pins of Each Switching Mode Regulator. Apply out-

put load between these pins and GND pins. Recommend

placing output decoupling capacitance directly between

these pins and GND pins.

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

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