MSM7664 datasheet(49/76 Pages) OKI

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MSM7664

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PEDL7664-01

OMR[7]

HSYNC output timing select *0: HSYNC output signal is detected near sync

threshold and sync tip.

1: HSYNC output signal is detected at sync

threshold setting position.

Note:

When the HSYNC output signal is detected at sync threshold setting position, it is

hardly affected by noise.

OMR[6]

VSYNC output timing select *0: VSYNC_L is synchronized to HSYNC_L and

then output

1: VSYNC_L is output when a VSYNC input

signal is detected.

Note:

When a non-standard signal is decoded, the output is stabilized after the VSYNC_L

input signal is detected (setting 1).

OMR[5:3]

Undefined

Set to 0

OMR[2]

Hi-Z output in SLEEP mode

*0: Active

1: Hi-Z

Note:

This register selects either normal or Hi-Z as the output pin status in SLEEP mode.

OMR[1]

Status2 output mode

*0: NTSC/PAL identification

1: HLOCK sync detection

OMR[0]

Status3 output mode

*0: TV/VCR identification

1: CSYNC

Note:

OMR[1:0] correspond to the STATUS[2:3] output of output pins.

Default

Recommended Value

OMR[7] OMR[6] OMR[5] OMR[4] OMR[3] OMR[2] OMR[1] OMR[0]

Default

Recommended Value

OPCC[7] OPCC[6] OPCC[5] OPCC[4] OPCC[3] OPCC[2] OPCC[1] OPCC[0]

Output phase control for data C (OPCC)

Write only

<address: $0F>

OPCC[7]

Undefined

Set to 0

OPCC[6]

Anti-noise circuit

*0: OFF

1: ON

Note:

The stability is increased when this setting is made ON at the time of decoding signals

under weak electric fields.

OPCC[5:2]

Undefined

Set to 0

OPCC[1:0]

Output phase control for data C

*00: normal

01: forward l clock

10: backward 2 clock

11: backward l clock

Note:

The output phase of data C is controlled.

Optional Mode Register (OMR)

Write only

<address: $10>

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