MSM7664 datasheet(7/76 Pages) OKI

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MSM7664

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PEDL7664-01

PIN DESCRIPTIONS (continued)

Symbol

Type

Description

53 to 60

Y[7] to Y[0]

Data output

Y[7]: MSB, Y[0]: LSB

During ITU-RBT.656 output mode: YCbCr 8-bit data output

During 8-bit (YCbCr) output mode: YCbCr 8-bit data output

During 16-bit (YCbCr) output mode: Y 8-bit data output

During 24-bit RGB output mode: G 8-bit data output

Output mode is set by pin 27 or 28, or register MRA [7:6].

DVDD

—

Digital power supply

DGND

—

Digital ground

63 to 70

C[7] to C[0]

Data output

C[7]: MSB, C[0]: LSB

During ITU-RBT.656 output mode: Hi-Z

During 8-bit (YCbCr) output mode: Hi-Z

During 16-bit (YCbCr) output mode: CbCr 8-bit data output

During 24-bit RGB output mode: R 8-bit data output

Output mode is set by pin 27 or 28, or register MRA [7:6].

ODD/EVEN

Field display output

If field is odd, "H" is output.

HVALID

Horizontal valid pixel timing output pin

If section is valid, "H" is output.

VVALID

Vertical valid line timing output pin

If section is valid, "H" is output.

VSYNC_L

Vertical sync signal (V sync) output pin

HSYNC_L

Horizontal sync signal (H sync) output pin

CLKXO

Pixel clock output

During double-speed input mode (pin 42 = 0): One half of system clock

frequency is output.

During normal input mode (pin 42 = 1): The same frequency as system

clock frequency is output.

CLKX2O

System clock output

System clock input is directly output.

DGND

—

Digital ground

DVDD

—

Digital power supply

CLKX2

System clock input (selected by operation mode)

NTSC ITU-RBT.601

NTSC Square Pixel

NTSC 4fsc

PAL ITU-RBT.601

PAL Square Pixel

Normal input mode

13.5 MHz

12.272727 MHz

14.31818 MHz

13.5 MHz

14.75 MHz

Double-speed input mode

27 MHz

24.545454 MHz

28.63636 MHz

27 MHz

29.5 MHz

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