TLV840 datasheet(6/32 Pages) TI

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7.5 Electrical Characteristics

At 0.7 V ≤ VDD ≤ 6 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF

and over operating free-air temperature range –40

℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 100 mV/µs. Typical

values are at TA = 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

COMMON PARAMETERS

VDD

Input supply voltage

TLV840MAxL

0.7

VIT–

Negative-going input threshold accuracy

(1)

VIT- = 0.8 V to 1.7 V

–2.5

±0.5

2.5

VIT- = 1.8 V to 5.4 V

–2

±0.5

VHYS

Hysteresis on VIT– pin

2.5

IDD

Supply current into VDD pin (2)

VDD = 2 V; VIT– = 0.8 V to 1.8 V

0.12

1.0

µA

VDD = 6 V; VIT– = 0.8 V to 5.4 V

0.15

1.2

VMR_L

Manual reset logic low input (2)

0.3VDD

VMR_H

Manual reset logic high input (2)

0.7VDD

RMR

Manual reset internal pull-up resistance

100

kΩ

RCT

CT pin internal resistance

500

kΩ

TLV840MADL (Open-drain active-low)

VPOR

Power on Reset Voltage (3)

VOL(max) = 300 mV

IOUT(Sink) = 15 µA

700

VOL

Low level output voltage

VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 V

IOUT(Sink) = 15 µA

300

VDD =1.5 V, 1.6 V ≤ VIT– ≤ 3.3 V

IOUT(Sink) = 500 µA

300

VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 V

IOUT(Sink) = 2 mA

300

Ilkg(OD)

Open-Drain output leakage current

VDD = VPULLUP = 6V

TA = –40℃ to 85℃

100

VDD = VPULLUP = 6V

350

TLV840MAPL (Push-pull active-low)

VPOR

Power on Reset Voltage (3)

VOL(max) = 300 mV

IOUT(Sink) = 15 µA

700

VOL

Low level output voltage

VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 V

IOUT(Sink) = 15 µA

300

VDD = 1.5 V, 1.6 V ≤ VIT– ≤ 3.3 V

IOUT(Sink) = 500 µA

300

VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 V

IOUT(Sink) = 2 mA

300

VOH

High level output voltage

VDD = 1.8 V, 0.8 V ≤ VIT– ≤ 1.4 V

IOUT(Source) = 500 µA

0.8VDD

VDD = 3.3 V, 1.5 V ≤ VIT– ≤ 3.0 V

IOUT(Source) = 500 µA

0.8VDD

VDD = 6 V, 3.1 V ≤ VIT– ≤ 5.5 V

IOUT(Source) = 2 mA

0.8VDD

TLV840-Q1

SNVSBY3A – NOVEMBER 2020 – REVISED APRIL 2021

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