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TLV840 Datasheet(PDF) 17 Page - Texas Instruments |
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TLV840 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 32 page ![]() 8.4 Device Functional Modes Table 8-1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic low is represented by "L". Table 8-1. Truth Table VDD MR RESET RESET VDD < VPOR Ignored Undefined Undefined VPOR < VDD < VIT- Ignored H L VDD ≥ VIT- L H L VDD ≥ VIT- H L H VDD ≥ VIT- Floating L H 8.4.1 Normal Operation (VDD > VPOR) When VDD is greater than VPOR, the reset signal is determined by the voltage on the VDD pin with respect to the trip point (VIT-) • MR high: the reset signal corresponds to VDD with respect to the threshold voltage. • MR low: in this mode, the reset is asserted regardless of the threshold voltage. 8.4.2 Below Power-On-Reset (VDD < VPOR) When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the asserted output low or high and reset voltage level is undefined. www.ti.com TLV840-Q1 SNVSBY3A – NOVEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV840-Q1 |
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