9.2.1.1 Design Requirements

This design requires voltage supervision on two separate rails: 3.3-V and 1.2-V rails. The voltage rail needs to

sequence upon power up with the 3.3-V rail coming up first followed by the 1.2-V rail at least 25 ms after.

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Two Rail Voltage Supervision

Monitor 3.3-V and 1.2-V rails

Two TLV840-Q1 devices provide voltage

monitoring with 1% accuracy with device options

available in 0.1 V variations

Voltage Rail Sequencing

Power up the 3.3-V rail first followed by 1.2-V rail

25 ms after

The CT capacitor on TLV840MAPL29-Q1 is set to

0.047 µF for a reset time delay of 29 ms typical

Maximum device current

consumption

1 µA

Each TLV840-Q1 requires 120 nA typical

9.2.1.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the supply voltage of the

microprocessor. The TLV840-Q1 can monitor any voltage between 0.8 V and 5.4 V. Depending on how far

away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct

voltage supervisor variant to choose. In this example, the first TLV840-Q1 triggers when the 3.3-V rail falls to

2.9 V. The second TLV840-Q1 triggers a reset when the 1.2-V rail falls to 0.9 V. The secondary constraint

for this application is the reset time delay that must be at least 25 ms to allow the microprocessor, and all

other devices using the 3.3-V rail, enough time to startup correctly before the 1.2-V rail is enabled via the

LDO. Because a minimum time is required, the user must account for capacitor tolerance. For applications with

Equation 2. Solving Equation 2 for 25 ms gives a minimum capacitor value of 0.0403 µF which is rounded up to

a standard value 0.047 µF to account for capacitor tolerance.

A 1 µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor

limit given the Isink possible at the expected supply voltage. In this design example nominal VDD is 1.2 V but

9.2.1.3 Application Curves

VDD

RESET

(LDO Enable)

V

(LDO)

OUT

30ms delay from VDD (3.3 V) to LDO Enable set by 0.047 µF on CT of TLV840MAPL29-Q1

Figure 9-2. Startup Sequence Highlighting the Delay Between 3.3 V and 1.2 V Rails

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TLV840-Q1

SNVSBY3A – NOVEMBER 2020 – REVISED APRIL 2021

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Product Folder Links: TLV840-Q1