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TLV840 Datasheet(PDF) 13 Page - Texas Instruments |
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TLV840 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 32 page ![]() 8.3.1.1 VDD Hysteresis The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD pin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis (VHYS) the output reset is deasserted after tD delay. VDD Hystersis Width VIT+ VIT- RESET RESET VDD Hystersis Width VIT+ VIT- Figure 8-1. Hysteresis Diagram 8.3.1.2 VDD Transient Immunity The TLV840-Q1 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends on both pulse duration (tGI_VIT-) found in Section 7.6 and overdrive. Overdrive is defined by how much VDD deviates from the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1. Overdrive = | [(VDD / VIT-) – 1] × 100% | (1) Overdrive Pulse Duration VDD V IT- V IT+ Figure 8-2. Overdrive vs Pulse Duration www.ti.com TLV840-Q1 SNVSBY3A – NOVEMBER 2020 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV840-Q1 |
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