TLV840 datasheet(16/32 Pages) TI

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8.3.4 Output Logic

8.3.4.1 RESET Output, Active-Low

RESET (Active-Low) applies to TLV840DL-Q1 (Open-Drain) and TLV840PL-Q1 (Push-Pull) hence the "L" in the

device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and the

MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then

RESET is asserted.

When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for the

specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high

voltage (VOH).

The TLV840DL-Q1 (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up

resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and

RESET can be pulled up to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltage

levels, give some consideration when choosing the pull-up resistor values. The external pull-up resistor value

determines the actual VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).

The Push-Pull variants (TLV840PL-Q1 and TLV840PH-Q1), denoted with "P" in the device name, does not

require an external pull-up resistor.

8.3.4.2 RESET Output, Active-High

RESET (Active-High), denoted with no bar above the pin label, applies to TLV840DH-Q1 (Open-Drain)

and TLV840PH-Q1 push-pull active-high version, hence the "H" in the device name. RESET remains low

(deasserted) as long as VDD is above the negative threshold (VIT-) and the MR pin is floating or above VMR_H. If

VDD falls below the negative threshold (VIT-) or if MR is driven low, then RESET is asserted driving the RESET

pin to high voltage (VOH).

When MR is again logic high or floating and VDD rise above VIT+ the delay circuit will hold RESET high for the

specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic low

voltage (VOL).

The TLV840DH-Q1 (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up

resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and

RESET can be pulled up to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltage

levels, give some consideration when choosing the pull-up resistor values. The external pull-up resistor value

determines the actual VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).

The Push-Pull variants (TLV840PL-Q1 and TLV840PH-Q1), denoted with "P" in the device name, does not

require an external pull-up resistor.

TLV840-Q1

SNVSBY3A – NOVEMBER 2020 – REVISED APRIL 2021

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TLV840 Datasheet(PDF) 16 Page - Texas Instruments