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AS5013 Datasheet(PDF) 34 Page - ams AG

Part # AS5013
Description  Low Power Integrated Hall IC for Human Interface Applications
PDF  50 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS5013 Datasheet(HTML) 34 Page - ams AG

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Page 34
ams Datasheet
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[v2-00] 2021-Apr-19
AS5013 − I²C Registers
Figure 38:
Power-Up Sequence
Registers Initialization
After Power Up, the following sequence must be performed:
1.
VDD and VDDp Power up, and reached their nominal
values (VDD>2.7V, VDDp>1.7V).
2.
RESETn LOW during >100ns
3.
Delay 1000μs
4.
Loop check register [0Fh] until the value F0h or F1h is
present (reset finished, registers to their default values)
5.
Optional: Write value 86h into register [2Eh]
Invert
magnet polarity. See Control Register 2 (2Eh) on page
22.
6.
Configure register [2Bh]
Configure M_ctrl middle Hall
element control
7.
Configure register [2Ch]
Configure J_ctrl attenuation
factor
8.
Configure register [2Dh]
Configure T_ctrl scaling
factor
9.
Configure the wanted Power Mode into register [0Fh]
(Idle mode or Low Power Mode with Timebase
configuration)
10. X Y coordinates are ready to be read.
Note: In order to detect if the magnet polarity is correct, read
the C5 middle Hall element when the magnet is centered.
C5 = (C5_pos – C5_neg) / 2
With: C5_pos = (c5_pos[11:8] << 8) | c5_pos[7:0]
C5_neg = (c5_neg[11:8] << 8) | c5_neg[7:0]
C5 must always be positive.
If C5 is negative, then invert the bit inv_spinning in the Control
Register 2 (2Eh). C5 will become positive.
External RESETn pin, and without Power on Reset (POR)
0V
2.7V
0
VDDp
(>1.7V)
VDD
RESETn
>100ns
>1000us
Power on Reset (POR) only
0V
0.2V
VDD
>1000us
Power up phase
VDD @ t=0 between
0V and 0.2V
2.7V
Power up phase
VDD @ t=0 between 0V
and 2.7V



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