DMA2286 datasheet(10/48 Pages) MICRONAS

10 / 48 page

DMA 2275, DMA 2286

7. Packet Processor

The packet processor is loaded via the scrambled pack-

et data input with packets of one subframe delivered by

the DMA 2271 or DMA 2281 and additionally has an in-

ternal connection to the deinterleaver of the DMA 2286

for packets of the other subframe. Packet data on these

lines are already spectrum descrambled and deinter-

leaved. The packet header and the PT byte have already

been corrected. The transmission of each packet starts

with a ‘0’ bit followed by 751 bit packet data with a unique

bit rate of 10.125 MHz (for C–, D– and D2–MAC).

To avoid simultaneous reception of two packets from dif-

ferent subframes, the packet output of the DMA 2286

has to be delayed in reference to the packet output of the

DMA 2281. This can be done with the CD bit in IM_Bus

The packet processor consists of:

– Packet Acquisition

– Packet Descrambler

7.1. Packet Acquisition

Task of the packet acquisition is to select specific pack-

ets out of the packet multiplex. In case of C– or D–MAC

packets can be located in one or two subframes, there-

fore, the packet selection will be repeated in the second

subframe if necessary. The selected packets can be er-

ror corrected if needed and are stored into packet buff-

ers which are located in the acquisition DRAM.

Due to timing conflicts with the line 625 acquisition, it is

not possible to acquire packets in the last (82nd) packet

slot of each subframe.

Additionally, all packets of both subframes are available

on a separate output pin (corrected packet data output),

only that the selected packets are replaced by their error

corrected equivalents.

The most common application of the packet acquisition

will be the selection of the following packets:

– ‘0’ packets

– EMM packets

– ECM packets

– BI packets

– 2nd level teletext packets

– general purpose data packets

The ‘0’ packets are forming the service identification (SI)

channel. The first thing the receiver software has to do

is to monitor the SI channel and to configure the receiver

according to the SI information. ‘0’ packets are either

hamming protected (H[8,4]) or golay protected (Golay

[24,12]). The SI channel is subdivided into 16 data

groups which can be identified by the data group (TG)

byte immediately following the PT byte of the packet

header.

The EMM and ECM packets are essentially carrying en-

cryption keys and control words. Their packet addresses

are indicated by the LISTX, ACMM and ACCM parame-

ters of the service identification channel. EMM packets

can be addressed to a single customer or a group of cus-

tomers by means of an address extension field of up to

36 bit, immediately following the PT byte. EMM and

ECM packets are highly error protected (Golay [24,12]

or Hamming [8,4]).

BI packets are carrying additional interpretation data re-

lated to sound packets with the same packet address.

They are selected by their PT byte (‘00’ or ‘3F’). BI pack-

ets are not error corrected.

Second level teletext packets can be selected to do

Golay [24,12] correction. They are available then on the

corrected packet data output which can be connected to

the teletext processor TPU 2740.

Every selected packet is CRC checked regardless of

packet type and error protection. The CRC check is

done over the full range of 720 bit and does not change

any packet data. CRC check, Golay [24,12] and Ham-

ming [8,4] error correction is done in real time, i.e. with

10.125 MHz. In case of packets with Golay [24,12] error

protection, the protection bits will be removed before

storing these packets into the packet buffer. the packet

length is therefore reduced from 96 bytes (full length

packet) to 48 bytes (half length packets), doubling the

possible number of packets in the related packet buffer.

The result of CRC check and the number of uncorrect-

able Golay or Hamming codes per packet is indicated in

a special packet error buffer which holds up to 16 error

bytes for every packet buffer. In case of full length pack-

ets, only every second entry of the error buffer is used.

Every selected packet is stored into the external acquisi-

tion DRAM of the descrambler chip. The DRAM includes

8 independent packet buffers, each offering the data ca-

pacity to store 8 full length packets or 16 half length

packets. The packet buffers can be read out by software

at any time and in any sequence. There are two ways to

use these packet buffers. One is the “standard” buffer

application where the buffer is automatically closed

when it is filled up with packets. The buffer must then be

reopened by software to start packet acquisition again.

The second way is the “ring” buffer application where the

packet buffer is always open and the oldest packets in

the buffer are overwritten by the next incoming packets.

Each packet buffer can be monitored by reading its buff-

er status. The buffer status is located in the FP memory

and includes a buffer pointer (bit 4–0) which indicates

the position where the next packet will be stored in num-

bers of half length packets. In ring buffer application this

pointer runs modulo 16 and in standard buffer applica-

tion the pointer stops at 16.

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