DMA2286 datasheet(11/48 Pages) MICRONAS

11 / 48 page

DMA 2275, DMA 2286

The buffer application (standard/ring) can be defined

with bit 5 in the buffer status register. Bit 7 allows to close

or reopen the buffer under software control. Bit 6 defines

the buffer increment. that means whether the buffer will

store full length (96 byte) packets or half length (48 byte)

packets.

Each of the 8 packet buffer is attached to a program-

mable packet filter which selects specific packets out of

the packet multiplex depending on packet address (PA),

continuity index (CI), packet type (PT) and packet ad-

dress extension (PAE). The packet address extension

can be used to select EMM packets by their specific cus-

tomer address (UCA, SCA, CCA) or to select ECM pack-

ets by command identification (CI or to select the data

group type (TG) of ‘0’ packets. This selection is done af-

ter error correction.

Each of the 8 packet filter is controlled by a set of regis-

ters located in the acquisition DRAM and programmable

by software. The ‘packet address base’ (PAB) registers

define the 10 bit packet address and the continuity in-

dex. The ‘packet address extension’ (PAE) registers de-

fine up to 36 bit of the address extension field. The ‘pack-

et selection control’ (PSC) registers define how packets

will be selected, error corrected and linked together.

The software should take care of conflicts like program-

ming different packet filters with the same conditions.

There must be at least one difference in the combination

of packet address, continuity index, packet type, and

packet location. Otherwise the result of the packet selec-

tion will be undefined.

If packet link is activated, the first packet meeting all pro-

grammed conditions is defined as sync packet. Selec-

tion of continuation packets is done according to the

packet link status. In case of CI link, the continuity index

of following packets will be ignored. In case of PT link,

the packet type selection is changed to PT2. a special bit

in the buffer status indicates if this procedure has been

activated by the first sync packet. The packets are then

stored into the packet buffer in the same order as they

are transmitted. The choice of packet link is independent

from the choice of buffer application.

Depending on the page select bit in the PSC register the

packet address extension is checked in every packet or

only in the sync packet. To select linked EMM packets by

customer address this bit should be ‘0’, to select linked

‘0’ packets by data group type this bit should be ‘1’.

7.2. Packet Descrambler

Main task of the packet descrambler is to detect those

sound or data packets that have to be descrambled.

Four different packet addresses can be recognized. Af-

ter detection of such a packet the concerning PRBS 3

generator is selected and produces an output sequence

of 720 bit to descramble the packet data. The PT–Byte

of each selected packet is decoded to disable the PRBS

3 generator output in case of BI packets (‘00’ or ‘3F’).

The packet descrambler can be switched to “automatic”

operation. In this mode the 4 center bits of the packet ad-

dress are ignored by the packet address comparator.

In case of C– or D–MAC, packets carrying one digital

component can be inserted in one or both subframes,

therefore the packet recognition will be repeated in the

second subframe if necessary.

Because the packet header is not scrambled, the packet

recognition has about 20 clock cycles to compare the

packet address before start of the descrambling se-

quence. Therefore there is only a 4 clock cycle delay be-

tween packet input and output.

Additionally, a packet gate is provided to remove pack-

ets form the packet output in case of denied access to

that particular service. These packets are not physically

removed – only the 720 bits after the packet header are

set to ‘1’.

Any other packet not selected by the packet recognition

passes through the packet descrambler unaffected but

with a delay of 4 clock periods.

The packet recognition is controlled by a set of registers

located in the acquisition DRAM and programmable by

software. The ‘scrambled packet address’ (SPA) regis-

ters define the 10 bit packet address and the ‘scrambled

packet status’ (SPS) registers define packet location

and status.

The software should take care of conflicts like program-

ming different SPA and SPS registers in the combination

of packet address and packet location. Otherwise, the

result of the packet recognition will be undefined.

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