DMA2286 datasheet(13/48 Pages) MICRONAS

13 / 48 page

DMA 2275, DMA 2286

8.2. IM Bus Interface

The INTERMETALL Bus (IM Bus for short) was de-

signed to control the DIGIT 2000 ICs by the CCU Central

Control Unit. Via this bus the CCU can write data to the

ICs or read data from them. This means the CCU acts

as a master, whereas all controlled ICs have purely

slave status.

The IM bus consists of three lines for the signals Ident

(ID), Clock (CL) and Data (D). The clock frequency

range is 50 Hz to 1 MHz. Ident and clock are unidirec-

tional from the CCU to the slave ICs, Data is bidirection-

al. Bidirectionality is achieved by using open–drain out-

puts. The 2.5 ... 1 kOhm pull–up resistor common to all

outputs must be connected externally.

The timing of a complete IM Bus transaction is shown in

Fig. 9–12. In the non–operative state the signals of all

three bus lines are High. To start a transaction the CCU

sets the ID signal to Low level, indicating an address

transmission, and sets the CL signal to Low level, as well

as to switch the first bit on the Data line. Then eight ad-

dress bits are transmitted, beginning with the LSB. Data

takeover in the slave ICs occurs at the positive edge of

the clock signal. At the end of the address byte the ID sig-

nal switches to High, initiating the address comparison

in the slave circuits. In the addressed slave, the IM bus

interface switches over to Data read or write, because

these functions are correlated to the address. Also con-

trolled by the address the CCU now transmits eight or

sixteen clock pulses, and accordingly one or two bytes

of data are written into the addressed IC or read out from

it, beginning with the LSB.

The completion of the bus transaction is signalled by a

short Low state pulse of the ID signal. This initiates the

storing of the transferred data.

For future software compatibility, the CCU must write a

zero into all bits not used at present. Reading undefined

or unused bits, the CCU must adopt “don’t” care behav-

ior.

8.2.1. IM Bus Addresses and Instructions

On the DMA 2275 or DMA 2286 the IM bus registers

5–10 are used to transfer data to and from the acquisi-

tion DRAM. This is done by subaddressing. Each data

transfer is preceded by the transfer of the extension ad-

dress highbyte and the read or write address lowbyte.

The subsequent data is written to or read from the

DRAM according to the preceding address command.

The DRAM address is then incremented internally to

prepare for the next data transfer (auto address incre-

ment). The status register is used to synchronize the

data transfer between CCU and the descrambler in

terms of handshaking. For this purpose the CCU has to

read the busy bit and has to wait until this bit is cleared.

Reading the busy bit can be done with a normal IM bus

read access which takes 16 IM Bus clock cycles or by

checking the IM Bus busy signal at pin 47 which delivers

the busy bit as a physical signal.

The same IM Bus registers can be used to transfer data

to and from the FP internal memory. Loading the write

address register (6) with an 8 bit FP address and setting

bit 10 at the same time writes the 12 bit content of the ex-

tension address register (5) into the FP RAM. Loading

the read address register (7) with an 8 bit FP address

and setting bit 10 at the same time starts transfer of 12

bit FP data into the data (8) and status (9) register. The

8 LSBs are copied into the data register in normal order

and the 4 MSBs are copied into the extension data of the

status register but in reversed order.

The DMA 2286 carries a second set of IM Bus registers,

which are used to control the sound processing. These

IM Bus registers are a copy of the registers of the DMA

2281 with identical functions and addresses (194–198,

203–206 and 208–210). The CCU selects the IM Bus

registers of the descrambler chip by writing ‘1’ into the

chip select register 198. This disables all parallel IM Bus

registers of the decoder chip except the chip select reg-

ister. Writing ‘0’ into the chip select register disables all

IM Bus registers of the descrambler chip, except the

subaddressing registers 5–10 and the chip select regis-

ter 198.

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